1. Field of the Invention
The present invention relates generally to a data processor having a branch predicting function and more particularly, to a data processor having a pipeline mechanism and a branch predicting function for predicting whether an instruction will be branched or not at the time of decoding.
2. Description of the Background Art
Instructions of the computer include a non-branch instruction, an unconditional branch instruction and a conditional branch instruction. The conditional branch instruction is an instruction which causes a branch when a certain condition is satisfied, which instruction constitutes a barrier to speeding up of the computer of a pipeline system. Therefore, a branch predicting system for predicting whether a branch will occur or not when the conditional branch instruction is applied is used. Such a branch predicting method is described in "COMPUTER", January 1984. issued by IEEE COMPUTER SOCIETY.
FIG. 1 is a schematic block diagram showing a conventional data processor having a branch predicting function. Referring now to FIG. 1, description is made on a structure of the conventional data processor having a branch predicting function. An instruction register 1 stores an instruction outputted to a data bus. The instruction stored in the instruction register 1 is applied to an instruction decoder 2. The instruction decoder 2 decodes the instruction and outputs an operation instructing signal, a signal indicative of a branch displacement (if the instruction is a conditional branch instruction or an unconditional branch instruction), and a signal indicative of an instruction length of the decoded instruction. An object computer 3 executes the instruction in response to the operation instructing signal outputted as a result of decoding of the instruction by the instruction decoder.
A branch predicting mechanism 4 stores a branch predicting bit corresponding to an address of the instruction. The branch predicting bit predicts whether a branch will occur or not when the instruction is executed. When the instruction is decoded, the branch predicting mechanism 4 reads out the branch predicting bit from an address corresponding to the instruction and applies the branch predicting bit to a comparator 5 and a next fetch instruction addressing portion 6. If a pre-branch operation predicting that a branch will occur, is performed, the comparator 5 compares the result predicted in response to the branch predicting bit with the result of execution, by the object computer 3, of conditional branch instruction in which a branch is predicted, and applies a branch prediction failure signal to the next fetch instruction addressing portion 6 when the results do not coincide with each other.
When a failure in branch prediction is determined by the comparator 5, the next fetch instruction addressing portion 6 reads out an instruction in a correct direction from a memory in response to the branch prediction failure signal. The next fetch instruction addressing portion 6 includes an adder 61, a decoding program counter 62 and a save register 63. The adder 61 adds the instruction length to the contents of the decoding program counter 62 every time an instruction is executed, and outputs an address signal of a next instruction to be fetched. In the next fetch instruction addressing portion 6, address data of the decoding program counter 62 is saved in the save register 63 when the branch predicting bit is applied from the branch predicting mechanism, and the branch displacement is added to the address data counted by the decoding program counter 62 by the adder 61.
The address data in the decoding program counter 62 is saved in the save register 63, in order to load again to the saved address data to the decoding program counter 62, add the instruction length to the address data and fetch an instruction in the next address, when the branch prediction fails.
FIG. 2 is a diagram for explaining a branch predicting function. Referring now to FIGS. 1 and 2, description is made on a branch predicting method when the conventional conditional branch instruction is applied. The address data in the decoding program counter 62 is outputted to an address bus as an address signal, and an instruction is read out from a certain address in a memory (not shown) and loaded into the instruction register 1. The instruction is decoded by the decoder 2, so that the operation instructing signal and the instruction length are outputted. The object computer 3 performs processing operation in response to the operation instructing signal.
The adder 61 adds the instruction length decoded by the instruction decoder 2 to the contents of the decoding program counter 62 and then, outputs an address signal of the instruction to be next fetched to the address bus. The address signal outputted from the decoding program counter 62 corresponds to the conditional branch instruction, so that the branch predicting bit stored corresponding to a part of the address is read out and applied to the next fetch instruction addressing portion 6. If and when it is predicted that the instruction will be branched and it is determined that the instruction is a conditional branch instruction as a result of decoding, the next fetch instruction addressing portion 6 determines that the instruction is branched, so that the contents of the decoding program counter 62 are saved in the save register. The adder 61 adds the branch displacement decoded by the instruction decoder 2 to the contents of the decoding program counter 62. More specifically, as shown in FIG. 2, a branch displacement b is added to an address a of the conditional branch instruction, so that an address signal indicating an address a+b of the destination to be branched is outputted. Instruction of the destination to be branched is read out from a memory in response to the address signal.
On the other hand, the object computer 3 executes the conditional branch instruction. The conditional branch instruction is an instruction which branches if a certain condition is satisfied and does not branch if the condition is not satisfied. For example, when the conditional branch instruction having a condition that it is branched if a Z (Zero) flag is up is executed, a branch occurs if the Z flag is up and a branch does not occur if the Z flag is down. If and when the conditional branch instruction was not branched as a result of execution thereof by the object computer 3, an executed result indicating signal which indicates that a branch did not occur is applied to the comparator 5. Since branch predicting information is applied to the comparator 5 from the branch predicting mechanism 4, the comparator 5 determines that both do not coincide with each other and applies a branch prediction failure signal to the next fetch instruction addressing portion 6. If the conditional branch instruction was not branched as a result of execution thereof, the next fetch instruction address portion 6 must execute the instruction in the next address a+c of the conditional branch instruction shown in FIG. 2. However, contents of the decoding program counter 62 is used to predict that the conditional branch instruction is to be branched and outputs the address signal indicating the address a+b of the destination to be branched, as described above. Thus, the next fetch instruction addressing portion 6 cancels the contents of the decoding program counter 62, reads out the original address saved in the save register 63, and loads the original address to the decoding program counter 62. In addition, the adder 61 adds an instruction length c to the contents of the decoding program counter 62 and outputs the address signal indicating the address a+c. Thus, an instruction corresponding to the address a+c is read out from a memory and executed by the object computer 3.
Although the data processor having the conventional branch predicting function is constructed as described above, the address saved in the save register 63 must be transferred to the decoding program counter 62 and the instruction length must be added to the address when the branch prediction fails, so that processing becomes complicated.